1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which dynamic random access memory (DRAM) and logical circuit are arranged.
2. Description of Related Art
FIG. 10 is a sectional view showing the structure of a semiconductor device in which DRAM and logical circuit are arranged. In FIG. 10, numeral number 1 indicates a semiconductor device (hereinafter, denoting an embedded DRAM, and called eRAM for short). 2 indicates a memory cell unit of a DRAM, 3 indicates the whole field other than the memory cell unit 2 of the DRAM. In the field 3 other than the memory cell unit 2 of the DRAM, a logical circuit and a peripheral circuit of the DRAM are arranged.
Also, 11 indicates a silicon substrate. 12 indicates a bottom n-type (N) well. 13 indicates each of two p-type (P) wells. 14 indicates each of P wells. 15 indicates each of two N wells. 16 indicates an element isolation oxide film. 17 and 18 respectively indicate Nxe2x88x92 diffusion layers. 19 indicates an N+ diffusion layer. 20 indicates a Pxe2x88x92 diffusion layer. 21 indicates a P+ diffusion layer. 22 to 25 respectively indicate gate electrodes formed in two-layer structure. A plurality of insulation films 22a to 25a are respectively arranged on the gate electrodes 22 to 25. 26 indicates a first side wall of both the gate electrode 24 and the insulation film 24a. 27 indicates a second side wall of both the gate electrode 25 and the insulation film 25a. 28 indicates a bit line. 29 indicates a bottom-of-capacitor electrode. 30 indicates a top-of-capacitor electrode. 31 indicates a dielectric film arranged between the bottom-of-capacitor electrode 29 and the top-of-capacitor electrode 30. 32 to 37 respectively indicate interlayer insulation films. 38 to 41 respectively indicate metallic wires. 42 indicates a contact hole. 43 to 45 respectively indicate via holes. 46 indicates a metallic layer embedded in the contact hole 42. 47 to 49 respectively indicate metallic layers embedded in the via holes 43 to 45. 50 indicates a glass coat.
In the memory cell unit 2 of the DRAM shown in FIG. 10, only principal elements of the memory cell unit 2 are shown. That is, an n-channel metal oxide semiconductor (NMOS) having the gate electrode 22 and a capacitor which is composed of the bottom-of-capacitor electrode 29, the top-of-capacitor electrode 30 and the dielectric film 31 connected with the Nxe2x88x92 diffusion layer 17 of the NMOS are shown in FIG. 10 as principal elements of the memory cell unit 2 of the DRAM. Also, the bit line 28 connected with the Nxe2x88x92 diffusion layer 17 of the NMOS and the gate electrode 23 composing an NMOS of another memory cell are shown in FIG. 10 as other principal elements of the memory cell unit 2 of the DRAM.
Also, in the field 3 other than the memory cell unit 2 of the DRAM shown in FIG. 10, only principal elements of the field 3 are shown in FIG. 10. That is, as shown in FIG. 10, an NMOS having the first side wall spacer 26 and a PMOS having the second side wall spacer 27 are arranged in the field 3 as a logical circuit or a peripheral circuit of the DRAM.
In the logical circuit of a conventional eRAM, to perform high speed operations, a silicide layer (not shown) formed of CoSi2 or the like is formed on both the N+ diffusion layer 19, which has the first side wall spacer 26 and functions as a source/drain diffusion layer of the NMOS, and the P+ diffusion layer 21 which has the second side wall spacer 27 and functions as a source/drain diffusion layer of the PMOS, to reduce resistance in each of the+ diffusion layer 19 and the P+ diffusion layer 21.
In contrast, in the peripheral circuit of the DRAM of the conventional eRAM, no silicide layer is formed on both the N+ diffusion layer 19, which has the first side wall spacer 26 and functions as a source/drain diffusion layer of the NMOS, and the P+ diffusion layer 21 which has the second side wall spacer 27 and functions as a source/drain diffusion layer of the PMOS. Here, in the peripheral circuit of the DRAM, in addition to a MOS transistor having a wall side spacer, a MOS transistor such as a high withstand-pressure MOS transistor having no side wall spacer exists.
Next, a conventional manufacturing method of the eRAM 1 shown in FIG. 10 will be described below.
FIG. 11A, FIG. 11B, FIG. 11C, FIG. 12A, FIG. 12B, FIG. 12C, FIG. 13A and FIG. 13B are respectively sectional views showing conventional steps of forming the eRAM in the step order. In FIG. 11A to FIG. 13B, steps of forming the NMOS arranged in the memory cell unit 2 of the DRAM are shown on the left side, and steps of forming both the NMOS with the first side wall spacer 26 and the PMOS with the second side wall spacer 27, which are arranged in the field 3 other than the memory cell unit 2 of the DRAM, are shown on the right side. However, in the peripheral circuit of the DRAM, no silicide layer is formed on both the N+ diffusion layer 19 having the first side wall spacer 26 and the P+ diffusion layer 21 having the second side wall spacer 27. Therefore, both the NMOS with the first side wall spacer 26 and the PMOS with the second side wall spacer 27 shown on the right side of the FIG. 12C, FIG. 13A and FIG. 13B are limited to those arranged in the logical circuit, and the steps of forming a silicide layer are shown in FIG. 12C, FIG. 13A and FIG. 13B. Here, in FIG. 11A to FIG. 13B, the bottom N well 12, the P wells 13 and 14, the N wells 15, a gate oxide film, the Nxe2x88x92 diffusion layers 17 and 18, the N+ diffusion layer 19, the Pxe2x88x92 diffusion layer 20 and the P+ diffusion layer 21 are omitted and not shown.
When eRAM is manufactured according to a conventional method, the bottom N well 12, the P wells 13 and 14 and the N wells 15 are initially formed in the silicon substrate 11. Thereafter, the element isolation oxide film 16 is formed in the silicon substrate 11. Thereafter, a gate oxide film is formed on the silicon substrate 11. Thereafter, the gate electrodes 22 to 25, on which the insulation films 22a to 25a are respectively arranged, are formed on the gate oxide film. Thereafter, to form the Nxe2x88x92 diffusion layers 17 and 18 respectively in the memory cell unit 2 of the DRAM and the field 3 other than the memory cell unit 2 of the DRAM, a resist pattern having a plurality of openings at prescribed positions is formed on the silicon substrate 11. Thereafter, ions of n-type impurity are injected into the silicon substrate 11 through the openings of the resist pattern, and the Nxe2x88x92 diffusion layers 17 and 18 are formed in an upper portion of the silicon substrate 11. Thereafter, the resist pattern is removed. Thereafter, to form the Pxe2x88x92 diffusion layer 20 in the field 3 other than the memory cell unit 2 of the DRAM, another resist pattern having an opening at a prescribed position is formed on the silicon substrate 11. Thereafter, ions of p-type impurity are injected into the silicon substrate 11 through the opening of the resist pattern, and the Pxe2x88x92 diffusion layer 20 is formed in the upper portion of the silicon substrate 11. Thereafter, the resist pattern is removed. Thereafter, a side wall spacer forming film 101 formed of silicon nitride film is deposited on the whole surface area (refer to FIG. 11A).
Thereafter, to form the N+ diffusion layer 19 as a source/drain diffusion layer of the NMOS in the field 3 other than the memory cell unit 2 of the DRAM, a first resist pattern 103 having an opening 102 at a prescribed position is formed on the side wall spacer forming film 101. Thereafter, anisotropic etching is performed for a portion of the side wall spacer forming film 101 which is exposed from the opening 102 of the first resist pattern 103, and the first side wall spacer 26 is formed on a side wall of the gate electrode 24 of the NMOS. Thereafter, ions of n-type impurity are injected into the silicon substrate 11 through the opening 102 of the first resist pattern 103, and the N+ diffusion layer 19 is formed in the upper portion of the silicon substrate 11 (refer to FIG. 11B). Thereafter, the first resist pattern 103 is removed.
Thereafter, to form the P+ diffusion layer 21 as a source/drain diffusion layer of the PMOS in the field 3 other than the memory cell unit 2 of the DRAM, a second resist pattern 105 having an opening 104 at a prescribed position is formed on the side wall spacer forming film 101. Thereafter, anisotropic etching is performed for a portion of the side wall spacer forming film 101 which is exposed from the openings 104 of the second resist pattern 105, and the second side wall spacer 27 is formed on a side wall of the gate electrode 25 of the PMOS. Thereafter, ions of p-type impurity are injected into the silicon substrate 11 through the opening 104 of the second resist pattern 105, and the P+ diffusion layer 21 is formed in the upper portion of the silicon substrate 11 (refer to FIG. 11C). Thereafter, the second resist pattern 105 is removed (refer to FIG. 12A).
Thereafter, a silicide protection film 106 is deposited on the whole surface area (refer to FIG. 12B). The silicide protection film 106 is formed of TEOS oxide film (that is, silicon oxide film made of tetra-ethyl-ortho-silicate material).
Thereafter, to form a silicide layer on both the N+ diffusion layer 19 of the NMOS having the first side wall spacer 26 and the P+ diffusion layer 21 of the PMOS having the second side wall spacer 27 in the logical circuit, a third resist pattern 108, which has a plurality of openings 107 at prescribed positions, is formed on the whole surface area so as to place the openings 107 on the N+ diffusion layer 19 and the P+ diffusion layer 21 through the silicide protection film 106. Thereafter, portions of the silicide protection film 106 exposed from the openings 107 of the third resist pattern 108 are removed by etching (refer to FIG. 12C). As a result, a first opening 109 placing on the N+ diffusion layer 19 and a second opening 110 placing on the P+ diffusion layer 21 are formed on the silicide protection film 106. Thereafter, the third resist pattern 108 is removed (refer to FIG. 13A).
Thereafter, a metallic film made of cobalt is deposited on the whole surface area. Thereafter, a silicide process is performed. That is, a first silicide layer 111 made of CoSi2 is formed on the N+ diffusion layer 19 of the NMOS exposed from the first opening 109, and a second silicide layer 112 made of CoSi2 is formed on the P+ diffusion layer 21 of the PMOS exposed from the second opening 110 (refer to FIG. 13B). In this silicide process, thermal processing is initially performed for the metallic film at a low temperature according to a ramp anneal method, and the metallic film deposited on both the N+ diffusion layer 19 and the P+ diffusion layer 21 is silicified. Thereafter, non-silicified metallic film is removed by etching. Thereafter, thermal processing is performed for the silicified metallic film at a high temperature, and a di-silicide metallic film is formed out of the silicified metallic film.
Thereafter, the silicide protection film 106 not yet removed is removed by etching. Thereafter, the interlayer insulation film 32 is deposited on the whole surface area. Thereafter, the other constituent elements shown in FIG. 10 are formed.
Therefore, in the logical circuit of the field 3, the eRAM is manufactured on condition that the silicide layers (or the di-silicide metallic film) made of CoSi2 are respectively formed on the N+ diffusion layer 19 of the NMOS having the first side wall spacer 26 and the P+ diffusion layer 21 of the PMOS having the second side wall spacer 27.
In the conventional manufacturing method of the eRAM performed according to the above-described steps, because characteristics of the silicide layer formed on the N+ diffusion layer 19 are the same as the characteristics of the silicide layer formed on the P+ diffusion layer 21 in the logical circuit, there is a problem that an optimum silicide layer, which has the characteristics (for example, diffusion resistance, junction leak current between diffusion layers, and contact resistance for diffusion layer) required for the eRAM, cannot be formed on each of the N+ diffusion layer 19 and the P+ diffusion layer 21.
Also, in the conventional manufacturing method of the eRAM, the silicide protection film is deposited after the formation of both the N+ diffusion layer 19 and the P+ diffusion layer 21. Therefore, there is another problem that a mask for forming the third resist pattern 108 used only to form the openings 109 and 110 in the silicide protection film is required and a mask matching operation is required for the mask.
A main object of the present invention is to provide, with due consideration to the drawbacks of the conventional manufacturing method of the eRAM, a manufacturing method of a semiconductor device in which a silicide layer having characteristics optimum to an N+ diffusion layer and a silicide layer having characteristics optimum to a P+ diffusion layer are formed.
Also, a subordinate object of the present invention is to provide a manufacturing method of a semiconductor device in which a mask for the formation of a resist pattern used only to form an opening in a silicide protection film is not required and the number of mask matching operations is reduced.
The main object and the subordinate object are achieved by the provision of a manufacturing method of a semiconductor device, in which a dynamic random access memory and a logical circuit are arranged, comprising a step of depositing a side wall spacer forming film and a first silicide protection film after forming a gate electrode on a gate oxide film formed on a silicon substrate, a step of forming a first resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a first conductive channel MOS transistor after depositing the first silicide protection film, a step of removing a portion of the first silicide protection film exposed from the opening of the first resist pattern after the formation of the first resist pattern to form a first opening in the first silicide protection film, a step of forming a fist side wall spacer on a side wall of a gate electrode of the first conductive channel MOS transistor after the formation of the first opening and forming the source/drain diffusion layer of the first conductive channel MOS transistor, a step of removing the first resist pattern and forming a first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor exposed from the first opening of the first silicide protection film, a step of depositing a second silicide protection film after the formation of the first silicide layer, a step of forming a second resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a second conductive channel MOS transistor after depositing the second silicide protection film, a step of removing a portion of the second silicide protection film and a portion of the first silicide protection film exposed from the opening of the second resist pattern after the formation of the second resist pattern to form a second opening penetrating the second silicide protection film and the first silicide protection film, a step of forming a second side wall spacer on a side wall of a gate electrode of the second conductive channel MOS transistor after the formation of the second opening and forming the source/drain diffusion layer of the second conductive channel MOS transistor, and a step of removing the second resist pattern and forming a second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor exposed from the second opening of both the second silicide protection film and the first silicide protection film.
In the above steps, the step of forming the first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor differs from the step of forming the second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor. Also, no resist pattern is used only to form the opening in the silicide protection film.
Accordingly, a silicide layer having characteristics optimum to the source/drain diffusion layer of the first conductive channel MOS transistor and a silicide layer having characteristics optimum to the source/drain diffusion layer of the second conductive channel MOS transistor can be formed. Also, a mask for the formation of a resist pattern used only to form the opening in the silicide protection film is not required, and the number of mask matching operations can be reduced.
The main object and the subordinate object are also achieved by the provision of a manufacturing method of a semiconductor device, in which a dynamic random access memory and a logical circuit are arranged, comprising a step of depositing a side wall spacer forming film and a silicide protection film after forming a gate electrode on a gate oxide film formed on a silicon substrate, a step of forming a first resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a first conductive channel MOS transistor after depositing the silicide protection film, a step of removing a portion of the silicide protection film exposed from the opening of the first resist pattern after the formation of the first resist pattern to form a first opening in the silicide protection film, a step of forming a fist side wall spacer on a side wall of a gate electrode of the first conductive channel MOS transistor after the formation of the first opening and forming the source/drain diffusion layer of the first conductive channel MOS transistor, a step of removing the first resist pattern and forming a first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor exposed from the first opening of the silicide protection film, a step of forming a second resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a second conductive channel MOS transistor after the formation of the first silicide layer, a step of removing a portion of the silicide protection film exposed from the opening of the second resist pattern after the formation of the second resist pattern to form a second opening in the silicide protection film, a step of forming a second side wall spacer on a side wall of a gate electrode of the second conductive channel MOS transistor after the formation of the second opening and forming the source/drain diffusion layer of the second conductive channel MOS transistor, and a step of removing the second resist pattern, forming a second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor exposed from the second opening of the silicide protection film and forming a third silicide layer on the first silicide layer exposed from the first opening of the silicide protection film.
In the above steps, the step of forming the first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor differs from the step of forming the second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor. Also, no resist pattern is used only to form the opening in the silicide protection film.
Accordingly, a silicide layer having characteristics optimum to the source/drain diffusion layer of the first conductive channel MOS transistor and a silicide layer having characteristics optimum to the source/drain diffusion layer of the second conductive channel MOS transistor can be formed. Also, a mask for the formation of a resist pattern used only to form the opening in the silicide protection film is not required, and the number of mask matching operations can be reduced.
The main object is achieved by the provision of a manufacturing method of a semiconductor device, in which a dynamic random access memory and a logical circuit are arranged, comprising a step of depositing a side wall spacer forming film after forming a gate electrode on a gate oxide film formed on a silicon substrate, a step of forming a first resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a first conductive channel MOS transistor after depositing the side wall spacer forming film, a step of forming a fist side wall spacer on a side wall of a gate electrode of the first conductive channel MOS transistor after the formation of the first resist pattern and forming the source/drain diffusion layer of the first conductive channel MOS transistor, a step of removing the first resist pattern and forming a second resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a second conductive channel MOS transistor, a step of forming a second side wall spacer on a side wall of a gate electrode of the second conductive channel MOS transistor after the formation of the second resist pattern and forming the source/drain diffusion layer of the second conductive channel MOS transistor, a step of removing the second resist pattern and depositing a silicide protection film, a step of forming a third resist pattern having a plurality openings so as to place one opening on the source/drain diffusion layer of the first conductive channel MOS transistor through the silicide protection film and to place another opening on the source/drain diffusion layer of the second conductive channel MOS transistor through the silicide protection film, a step of removing portions of the silicide protection film exposed from the openings of the third resist pattern after the formation of the third resist pattern to form both a first opening placing on the source/drain diffusion layer of the first conductive channel MOS transistor and a second opening placing on the source/drain diffusion layer of the second conductive channel MOS transistor in the silicide protection film, a step of forming a first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor exposed from the first opening of the silicide protection film and forming a second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor exposed from the second opening of the silicide protection film, a step of removing the second silicide layer, and a step of forming a third silicide layer in a space, from which the second silicide layer is removed and which is exposed from the second opening of the silicide protection film, and forming a fourth silicide layer on the first silicide layer exposed from the first opening of the silicide protection film.
In the above steps, the step of forming the first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor differs from the step of forming the second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor.
Accordingly, a silicide layer having characteristics optimum to the source/drain diffusion layer of the first conductive channel MOS transistor and a silicide layer having characteristics optimum to the source/drain diffusion layer of the second conductive channel MOS transistor can be formed.